Design and Analysis of 4-bit 1.2GS/s Low Power CMOS Clocked Flash ADC

High-quality, high-resolution flash ADCs are used in reliable VLSI (Very Large-Scale Integrated) circuits to minimize the power consumption. An analogue electrical signal is converted into a discrete-valued sequence by these ADCs. This paper proposes four-bit 1.2GS/s low-power Clocked Flash ADC (C-FADC). A Clocked-Improved Threshold Inverter Quantization (CITIQ) comparator, an Adaptive Bubble Free (ABF) logic circuit, and compact Binary Encoder (BE) all part of presented structure. clock network comparator circuit reduces skew jitters, while ABF detects corrects fourth order bubble faults detected from thermometer code, then BE transforms free code binary code. Tanner EDA with 250-nm Technology implement C-FADC. The proposed design achieves ENOB 3.56, uses 3.24 mW power, has FOM 0.274pJ/conv.-step at input frequency 85 MHz. suggested C-FADC differential integral nonlinearities ±0.65 LSB +0.45/-0.5 LSB, respectively.